The methodology for increasing the capacity of Flash memory, which is used in memory cards and SSD drives, has been the use of chip stacking. The reason for this is simple, waiting for the manufacturing nodes to allow a good enough capacity per chip can take forever. That is why for some time this part of 3D NAND technology has been advancing and the latest comes from Tokyo Electron, which has reached the 400 layers 3D NAND Flash.


Flash memory manufacturers have spent years wearing their elbows to break the only advantage hard drives have over solid-state drives, the cost per Esports Extrasbyte of memory. Since in the rest of the elements, latency and bandwidth, flash memory surpasses a traditional HDD in everything. The solution for it? The so-called 3D NAND that we have been seeing for some time from different manufacturers.

Tokyo Electron has succeeded in manufacturing 400-layer 3D NAND Flash memory

3D NAND 400 layers

The fact of adding more layers to a NAND Flash memory chip has a series of difficulties when it comes to reaching a certain number, especially due to the heat generated by the contact between the different chips that make up the stack. That is why Tokyo Electron has developed a process to manufacture 400-layer NAND Flash memory with the aim of increasing the storage capacity of SSDs and memory cards in the medium-term future. This being the first process with this capacity in the world.

Specifically, what they have developed has developed an innovative etching technology that can produce memory channel holes in 3D NAND devices with more than 400 layers. To understand what all this refers to, we must bear in mind that any integrated circuit made up of stacked chips requires communicating these through silicon pathways that cross the different layers vertically.


What happens when layers are added indiscriminately?

stickerless ssd

As we increase the number of layers in a memory chip, a series of problems appear, such as:

  • Increasing the number of layers can increase the possibility of interference between themand, therefore, of the reliability when storing data.
  • Due to increasing the length in vias through silicon or TSV, we can find ourselves in an increase not only in latency, but also in power consumption when accessing the furthest parts of the stack.
  • It does much more complex to manage memory cellswhich makes it difficult to access information, delete cells and implement error correction systems.
  • A greater number of layers makes chip reliability decreases.

That is why new manufacturing processes have to be created to allow having 400-layer NAND Flash memories, since using current technologies the different points that we have described as problems may appear. Which means chips for non-volatile storage much slower and less reliable than current ones. Which is counterproductive in a world where bandwidths are getting higher and higher.