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TSMC promises six times larger CPU and GPU with CoWoS-L

tsmc promises six times larger cpu and gpu with cowos l

TSMC has discussed its plans to create interposers or base chips with a size six times larger than current ones Under his CoWoS-L technology that will enable much more advanced high-performance server structures and architectures. What does this mean and how does it relate to the future of supercomputing? Will we see such technology being used in any technology?

An interposer or base die is a large chip on which others are mounted and which serves for communication between them. With the advent of the chiplet concept, based on breaking a CPU or GPU into several different pieces, it has become very popular, since it is the most effective way of communication, especially when we talk about products that require high bandwidth, due to the fact that it allows us to increase the number of contact pins and reduce the clock speed of each of them. The result? Less pJ of consumption per transmitted bit than a direct connection through a bus.


TSMC interposers six times larger with CoWoS-L

MI300 Interposers

However, one of the reasons why the chiplet philosophy has been adopted is that it allows us to break the lattice boundary. Since when printing a chip on a wafer we cannot exceed a certain limit. By dividing it into several pieces we can bypass this limitation. But what about the interposer or base chip underneath? Well, this must be much larger than the limit. It is currently 1.8 times the size.

Well, TSMC has just presented the development under its CoWoS-L technology of a new type of interposer with an area 6 times the size of the current reticle limit for conventional chips. Currently, said size is 858 mm², so a jump of this type would mean have a chip base on which to place different chips and memories of 5148 mm2. Of course, according to TSMC we will have to wait at least until 2025 to see the first products that use it.

They will be the basis for future superchips

Wafer Printing Chips

The technology that will enable interposers six times the size of the largest possible chip, at TSMC, It is not intended for the domestic market., but rather for the high performance computing or HPC market. As well as to face trends regarding artificial intelligence. So don’t think you’re going to see CoWoS-L technology on a PC chip or component.


Rather we should look at designs like Intel Ponte Vecchio either AMD Instinct graphics cards and especially the future MI300. Which are examples of designs beyond the size of the reticle and whose evolutions can benefit from a greater space. Of course, this will also mean an increase in average consumption, since increasing the size of the Base chip also increases the distances between its components and with it the consumption for communication.

However, this allows for many more chips to be placed in the entire lattice, as well as having a greater number of components and increasing performance with it. Therefore, the challenge for those who use these technologies will be to have a performance per watt of consumption that is high enough to justify said increase in the electricity bill of the servers that use this technology.


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