The problems for TSMC are increasing. We have been warning about it for some time, and now it is a confirmation that comes to us at a really important moment in the market. And it is because both AMD and NVIDIA are already thinking about the 3 nm of the Taiwanese, which will be one more step towards the barrier of GAA transistors. Why is this N3 so relevant? What makes them different? The answer is short and simple: SRAM’s scalability for the N3E and the N3X, that is, TSMC has a problem with the cache of the chips that it manufactures in the N3.
For some time now, they have gone from producing very expensive chips in the logical part of them, seeing how SRAM was tremendously cheap. The problems and limits of the architectures were never a problem with the cache as such, logic was always used to continue increasing performance, but… This has changed, and it has done so at the worst possible moment in the history of the lithographic processes.
TSMC and the problems with the SRAM (cache) in the nodes of N3, N4 and N5
We speculate with it due to some leaks and data referred to by TSMC itself, and again we are completely correct. WikiChip confirms our suspicions unfortunately for everyone: TSMC has a serious problem with SRAM (and the price). If you’ve been following us, you’ll be aware of (at least) part of why NVIDIA GPUs are priced higher than AMD’s.
The RDNA 3 architecture is much cheaper to build on MCM chips than the monodie used by NVIDIA. Because?
Well, by the mantra we’ve been repeating all the time: Cache is extremely expensive to implement on the N5 and 4N right now, so NVIDIA incurs much higher costs than AMD, but also gains a performance advantage.
For example, Navi 33 is slightly more expensive to manufacture per square millimeter than Navi 31, since the first one has the L3 included in the die and not in MCD, even though it is at 6 nm as the external cache. Having said this, what is the novelty of the argument that is now confirmed? Well, the forecasts we made they were more optimistic than reality.
A tiny scaling that will force AMD and NVIDIA to take action
What has been said with the N5 and the 4N is “optimistic” about what is to come. And it is that when TSMC presented the N3 and its variants, we already said that it was very strange that it did not talk about the scalability of its SRAM and only about logic. The reason is that their SRAM hardly scales.
It was said later that this would raise said scale by 1.2X, that is, a twenty% vs. N5, well, none of that is true. Today’s confirmation is much worse, since said scalability would be a maximum of 5%. Depending on the specific node, for example, N3B vs N3E, or N3E vs N3X, scalability against the current N5 is branded as zero. That value of 20% vs. 70% was not logical, mainly because scalability was impossible seeing the real value of the second.
Or what is the same, the density per square millimeter is improved in the logical part, but it is not reduced in the SRAM part of each chip. What does this mean? Well, a problem, in fact, a problem for anyone who contracts with TSMC for the N3. It means you increase the density per area in just over 15% compared to your previous node, but the improvement in the cache is negligible, in some cases none.
L2 will end up coming out of the main die at AMD and NVIDIA
Therefore, and once again, the cache is going to be more expensive to be able to couple it to the logic and its transistors, which is going to force AMD and NVIDIA to move quickly. Getting the L3 cache off-chip may only be the first step, and most likely L2 will also end up outside in a kind of MCD combined with both types.
To do this, the L0 and L1 have to scale in size to alleviate the deficiencies of the bus and latency, that is, we will see more of the same in GPU, but a step further, possibly with buses equal to or less than the same seriesall for the price of the GPU don’t shoot. On the other hand, there are many rumors of AMD and NVIDIA contracts with Samsung… We’ll see how this ends and how TSMC deals with the very problematic 2 nm seeing the problems with the N3 and the SRAM cache.