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Zen 4 will change the game in DDR5 RAM, these are the news

Not even two days have passed and we already have more news since the most optimal speed for RAM in the new AMD processors was leaked. And yes, those of Lisa Su will run with the disadvantage of not being able to scale in speed, but in exchange today we know that there are five key improvements that can tip the scales for the red team. These are the main novelties of Zen 4 for memory DDR5-RAM.

If the speed for the most optimal Ryzen 7000 is going to be DDR5-6000, Knowing that Intel is going to reach at least 6,600 MHz just by activating XMP and without voltage problems, such a move by AMD was to be expected, but perhaps we did not foresee as many changes as are going to be added in Zen 4.

Changes and news in Zen 4 with DDR5 RAM for Ryzen and EPYC processors

That said, we are going to see the six changes that the red team is going to introduce in its new processors, since they are changes in the architecture and not in the platform or product range, so any CPU that integrates Zen 4 to its credit will have. In addition, they are very interesting to analyze.

Independent memory channels

It will be a very important change, especially for those users who combine modules from different manufacturers, speed and latency, or simply for those who overclock high, very high or extreme. And it is that AMD is going to allow different timings per channel, be it A, B, C or D.

The advantages are easy to understand, since the IMC does not need to depend on a perfect squaring of tertiary and secondary timings, improving the compatibility of any RAM with its processors, something highly criticized and that has brought the company down the street of bitterness. for almost two years.

AMD EXPO and its two modes in Zen 4 with DDR5 RAM

Another important development on the basis that we expected EXPO works as XMP 3.0. This will not be the case for the most part, since it is announced that it will have two modes of operation:

  • Low latency mode.
  • High bandwidth mode.

In the news of the DDR5-6000 we commented: it is possible that the disadvantage of not reaching as high as Intel in bandwidth can be supplied with lower latency, which in the end is more beneficial for the AM5 platform, since it is intended for gaming.

Well, the low latency mode is going to hit the nail on the head in that paragraph, and maybe seeing Intel’s problems with P-Cores and E-Cores to homogenize the access time nanosecondsAMD is spot on despite having less bandwidth.

But for those who need it, High Bandwidth mode solves this problem, we understand that adding latency to the process.

Activate OC Tuner

It is not at all clear the functionality that it has beyond what has been commented: overclock limited by the power of the CPU or by its temperature. We understand that the IO Die is closely linked to the CCX and therefore to the temperature they reach so as not to force the CPU in general, since given the consumption rumors, as it happens in Intel, they will not be fresh, at least on paper.

It may be a new version of PBO more optimized that includes precisely the parameters of IO Die, we will have to wait to see what it is, although it seems that there will be no changes in this regard.

Asynchrony between CPU and PCIe clock

This is something highly anticipated without a doubt and that has its credit in the most custom and professional overclock. It also implies that by having different clocks, the frequency oscillations in the PCIe or its stabilization will have less influence on Infinity Fabricso it seems like a very successful step that we need more details to deepen.

CCX Clock Control

It is possibly the most striking and at the same time goes unnoticed. It seems that there will be independent control of the clock by full CCX, and at the same time it is named that it will be up to 4 of them.

As we have already seen in both Ryzen and EPYC, AMD will continue with the 8-core CCX for Zen 4, where the 7950X will include two CCDs for a total of 16 Cores. Well, a control of 4 CCX implies either configurations of smaller cores (something unlikely due to costs and physical space on the PCB) or processors of 32 cores, 64 cores and 96 cores controlled in groups of 1, 2 and 4 CCDs respectively with their different clocks.

It seems somewhat more focused on the EPYC range than the possibility that we will end up seeing a 32-core CPU on desktop for the mainstream. maybe for HEDT with Threadripper yes that is more than likely.

Host Clock in Zen 4

Little information for what we can expect or speculate. It looks like a clock control to overclock the IF or CCD, maybe for both, maybe a more exhaustive control of the IF itself. Nothing is clear.

Definitely, the changes are very interesting, especially in the RAM memory section, which is where AMD is going to lose from the start with Intel due to frequency. Perhaps this turns the tables and it is the red team that gets the best access time at the cost of bandwidth, which always squeezes more FPS in games, the main focus of the Zen 4 and DDR5 RAM.

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